View HT82A822R07_1154424.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HT82A822R USB Audio MCU
Features
* USB 2.0 full speed compatible * USB spec v1.1 full speed operation and USB audio * 1928 MCU type data memory RAM (Bank0) * 12884 Speaker Out Data RAM (Bank1, Bank2,
device class spec v1.0
* Operating voltage: fSYS= 6MHz/12MHz: 3.3V~5.5V * Low voltage reset function (3.0V0.3V) * High-performance 48kHz sampling rate for audio
Bank3, Bank4)
* 12884 MCU Type General Purpose Data RAM
(Bank5, Bank6, Bank7, Bank8)
* HALT function and wake-up feature reduce power
playback
* Embedded class AB power amplifier for speaker
consumption
* 24 bidirectional I/O lines (max.) * Two 16-bit programmable timer/event counter and
driving
* Embedded High Performance 16 bit audio DAC * Support digital volume control * HID support which can remote control of playback
overflow interrupts
* Watchdog Timer * 16-level subroutine nesting * Bit manipulation instruction * 15-bit table read instruction * 63 powerful instructions * All instructions in one or two machine cycles * 48-pin SSOP package
volume/mute
* 3 endpoints supported (endpoint 0 included) * Support 1 Control , 1 Interrupt , 1 Isochronous
transfer
* Total FIFO size are 400 byte (8, 8, 384 for EP0~EP2) * 409615 program memory ROM
General Description
This HT82A822R is an 8-bit high performance RISC-like microcontroller designed for USB Speaker product applications. The HT82A822R combines a 16-bit DAC, USB transceiver, SIE (Serial Interface Engine), audio class processing unit, FIFO, 8-bit MCU into a single chip. The DAC in the HT82A822R is operating at the 48kHz sampling rate. The HT82A822R has a digital programmable gain amplifier. The gain range is from -32dB to +6dB. The HT82A822R has a Human Interface Device function that allows a user to control the playback volume at the device side. The HT82A822R also can mute the analog output signal by the operation of HID buttons.
Rev. 1.10
1
June 29, 2007
HT82A822R
Block Diagram
STACK0 STACK1 STACK2 STAC K14 P ro g ra m ROM P ro g ra m C o u n te r STAC K15 IN T C TM R0 M U X In s tr u c tio n R e g is te r TM R0C MP M U X DATA M e m o ry W DTS W D T P r e s c a le r In s tr u c tio n D ecoder ALU T im in g G e n e ra to r S h ifte r MUX PAC STATUS PA PBC PB PCC PORT C PORT B PORT A PA0~PA7 W DT M U X fS /4 BP In te rru p t C ir c u it TM R1C M U X TM R1 fS
YS
/4 P C 1 /T M R 0
YS
P C 2 /T M R 1
E N /D IS fS
YS
/4
W DT OSC
PB0~PB7
OSCO
OSCI
ACC U S B 1 .1 X C V R
USBD+ USBDV33O
U S B 1 .1 F u ll S p e e d E n g in e
F IF O IS O P ro c e s s D ig ita l V o lu m e C o n tro l
PC
PC0 PC 3~PC 5
3 .3 V R e g u la to r
D A C W r ite D a ta MUX 1 6 - b it D /A Power Amp LO UT ROUT
Pin Assignment
PA3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PA2 PA1 PA0 AVDD2 ROUT LO UT AVSS2 AVSS1 B IA S AVDD1 DVSS3 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 DVSS2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 PA4 PA5 PA6 PA7 DVSS1 V33O USBDP USBDN DVDD1 RESET OSCO OSCI NC NC NC NC NC NC PC0 PC1 PC2 PC3 PC4 DVDD2
H T82A 822R 4 8 S S O P -A
Rev. 1.10
2
June 29, 2007
HT82A822R
Pin Description
Pin No. Pin Name 4~1, 48~45 5 6 7 8 9 10 11 12 20~13 PA0~PA7 I/O I/O Description Bidirectional 8-bit input/output port. Each bit can be configured as wake-up input by mask option. Software instructions determine the CMOS output or Schmitt trigger input with or without pull-high (by mask option). Audio power amplifier positive power supply, AVDD2 should be external connected to VDD. Right driver analog output Left driver analog output Audio power amplifier negative power supply, ground Audio DAC negative power supply, ground Connect a capacitor to ground to increase half-supply stability Audio DAC positive power supply Negative digital & I/O power supply, ground Bidirectional 8-bit input/output port. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by pull-high options, nibble option). Bidirectional 8-bit input/output port. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by pull-high options, nibble option). Negative digital & I/O power supply, ground Positive digital & I/O power supply No connection OSCI, OSCO are connected to an 6MHz or 12MHz crystal/resonator (determined by software instructions) for the internal system clock Schmitt trigger reset input, active low Positive digital power supply USBDN is USBD- line USB function is controlled by software control register USBDP is USBD+ line USB function is controlled by software control register 3.3V regulator output Negative digital power supply, ground
AVDD2 ROUT LOUT AVSS2 AVSS1 BIAS AVDD1 DVSS3 PB0~PB7
3/4 O O 3/4 3/4 O 3/4 3/4 I/O
23~21, PC0~PC7 30~26 24 25 36~31 37 38 39 40 41 42 43 44 DVSS2 DVDD2 NC OSCI OSCO RESET DVDD1 USBDN USBDP V33O DVSS1
I/O 3/4 3/4 3/4 I O I 3/4 I/O I/O O 3/4
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C IOH Total............................................................-100mA
Rev. 1.10
3
June 29, 2007
HT82A822R
D.C. Characteristics
Symbol VDD IDD ISTB VIL1 VIH1 VIL2 VIH2 IOL IOH RPH VLVR VV33O Parameter Operating Voltage Operating Current Standby Current Input Low Voltage for I/O Ports Input High Voltage for I/O Ports Input Low Voltage (RESET) Input High Voltage (RESET) I/O Port Sink Current I/O Port Source Current Pull-high Resistance Low Voltage Reset 3.3V Regulator Output Test Conditions VDD 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V IV33O=-5mA VOL=0.1VDD VOH=0.7VDD 3/4 3/4 Conditions 3/4 No load, fSYS=12MHz No load, system HALT, USB transceiver and 3.3V regulator on 3/4 3/4 3/4 3/4 Min. 3.3 3/4 3/4 0 0.7VDD 0 0.9VDD 3/4 3/4 30 2.7 3 Typ. 5 9 340 3/4 3/4 3/4 3/4 5 -5 40 3 3.3 Max. 5.5 3/4 3/4 0.3VDD VDD 0.4VDD VDD 3/4 3/4 80 3.3 3.6 Ta=25C Unit V mA mA V V V V mA mA kW V V
DAC+Power Amp: Test condition: Measurement bandwidth 20Hz to 20kHz, fS= 48kHz. Line output series capacitor with 220mF. THD+N THD+NNote1 4W load 5V 8W load SNR Signal to Noise RatioNote1 4W load 5V 8W load 4W load DR Dynamic Range 5V 8W load POUT 4W load, THD=10% Output Power 5V 8W load, THD=10% Note: 1. Sine wave input at 1kHz, -6dB 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 -30 -35 81 82 87 88 400 200 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 dB
dB
dB
mW/ch
A.C. Characteristics
Symbol fSYS Parameter System Clock (Crystal OSC) Test Conditions VDD 5V 5V 3/4 3/4 3/4 Conditions 3/4 3/4 3/4 3/4 3/4 Min. 0.4 3/4 1 3/4 1 Typ. 3/4 100 3/4 1024 3/4 Max. 12 3/4 3/4 3/4 3/4
Ta=25C Unit MHz ms ms tSYS ms
tWDTOSC Watchdog Oscillator Period tRES tSST tINT RESET Input Pulse Width System Start-up Timer Period Interrupt Pulse Width
Note: tSYS=1/fSYS
Rev. 1.10
4
June 29, 2007
HT82A822R
Functional Description
Execution Flow The system clock for the micro-controller is from a crystal oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to be effectively executed in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a full range of program memory. After accessing a program memory word to fetch an instruction code, the contents of the program counter are
S y s te m C lo c k T1 T2 T3 T4 T1 T2
incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading to the PCL register, performing a subroutine call or return from subroutine, initial reset, internal interrupt, external interrupt or return from interrupts, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within the current program ROM page. When a control transfer takes place, an additional dummy cycle is required.
T3 T4 T1 T2 T3 T4
O S C 2 ( R C o n ly ) PC PC PC+1 PC+2
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow Program Counter *11 0 0 0 0 0 *10 0 0 0 0 0 *9 0 0 0 0 0 *8 0 0 0 0 0 *7 0 0 0 0 0 *6 0 0 0 0 0 *5 0 0 0 0 0 *4 0 0 0 0 1 *3 0 0 1 1 0 *2 0 1 0 1 0 *1 0 0 0 0 0 *0 0 0 0 0 0
Mode Initial Reset External Interrupt Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow USB Interrupt Skip Loading PCL Jump, Call Branch Return from Subroutine
Program Counter+2 *11 #11 S11 *10 #10 S10 *9 #9 S9 *8 #8 S8 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0
Program Counter Note: *11~*0: Program counter bits #11~#0: Instruction code bits S11~S0: Stack register bits @7~@0: PCL bits
Rev. 1.10
5
June 29, 2007
HT82A822R
Program Memory - PROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 409615 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage:
* Location 000H
rupt is enabled and the stack is not full, the program begins execution at location 00CH.
* Table location
This area is reserved for program initialization. After a chip reset, the program always begins execution at location 000H.
* Location 004H
This area is reserved for the USB interrupt service program. If the USB interrupt is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004H.
* Location 008H
This area is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.
* Location 00CH
This location is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and the inter000H 004H 008H 00CH n00H nFFH D e v ic e In itia liz a tio n P r o g r a m U S B In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e L o o k - u p T a b le ( 2 5 6 W o r d s ) P ro g ra m M e m o ry
Any location in the program memory can be used as look-up tables. There are three method to read the ROM data by two table read instructions: TABRDC and TABRDL, transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining 1-bit words are read as 0. The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP, TBHP) is a read/write register (07H, 1FH), which indicates the table location. Before accessing the table, the location must be placed in the TBLP and TBHP (If the OTP option TBHP is disabled, the value in TBHP has no effect). The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt should be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory depending on the requirements. Stack Register - STACK This is a special part of the memory which is used to save the contents of the program counter only. The stack is organized into 16 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the proTable Location
FFFH
L o o k - u p T a b le ( 2 5 6 W o r d s ) 1 5 B its N o te : n ra n g e s fro m 0 to F
Program Memory
Instruction TABRDC [m] TABRDL [m]
*11 P11 1
*10 P10 1
*9 P9 1
*8 P8 1
*7 @7 @7
*6 @6 @6
*5 @5 @5
*4 @4 @4
*3 @3 @3
*2 @2 @2
*1 @1 @1
*0 @0 @0
Table Location Note: *11~*0: Table location bits @7~@0: Table pointer bits P11~P8: Current program counter bits when TBHP is disabled TBHP register bit3~bit0 when TBHP is enabled
Rev. 1.10
6
June 29, 2007
HT82A822R
gram counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent 16 return addresses are stored). Data Memory - RAM The data memory (RAM) is designed with 1928 bits. The data memory is divided into two functional groups: namely; special function registers 548 bits and general purpose data memory, Bank0: 1928 bits, Bank1~ Bank4: 12884 bits (Read Only), Bank5~Bank8: 12884 bits. Most are read/write, but some are read only. The special function registers include the indirect addressing registers (R0;00H, R1;02H), Bank register (BP, 04H), Timer/Event Counter 0 higher order byte register (TMR0H;0CH), Timer/Event Counter 0 lower order byte register (TMR0L;0DH), Timer/Event Counter 0 control register (TMR0C;0EH), Timer/Event Counter 1 higher order byte register (TMR1H;0FH), Timer/Event Counter 1 lower order byte register (TMR1L;10H), Timer/Event Counter 1 control register (TMR1C;11H), program counter lower-order byte register (PCL;06H), memory pointer registers (MP0;01H, MP1;03H), accumulator (ACC;05H), table pointer (TBLP;07H, TBHP;1FH), table higher-order byte register (TBLH;08H), status register ( S TAT U S ; 0 A H ) , i n t e r r u p t c o n t r o l r e g i s t e r 0 (INTC0;0BH), Watchdog Timer option setting register (WDTS;09H), I/O registers (PA;12H), I/O control registers (PAC;13H). Digital Volume Control Register (USVC;1CH). USB speaker flag register (USF;1DH), USB status and control register (USC;20H), USB endpoint interrupt status register (USR;21H), system clock control register (UCC;22H). Address and remote wakeup register (AWR;23H), STALL register(24H), SIES register (25H), MISC register(26H), SETIO register(27H), FIFO0~FIFO2 register (28H~2AH). DAC_Limit_L register (2DH), DAC_Limit_H register (2EH), DAC_WR register (2FH). The remaining space before the 40H is reserved for future expanded usage and reading these locations will get 00H. The general purpose data memory, addressed from 40H to FFH, is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations diB a n k 0 S p e c ia l R e g is te r
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 3FH 40H FFH D A C _ L im it_ L D A C _ L im it_ H DAC_W R TBHP USC USR UCC AW R STALL S IE S M IS C S E T IO F IF O 0 F IF O 1 F IF O 2 USVC USF
In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 BP ACC PCL TBLP TBLH W DTS STATUS IN T C 0 TM R0H TM R0L TM R0C TM R1H TM R1L TM R1C PA PAC PB PBC PC PCC
G e n e ra l P u rp o s e D a ta R A M (1 9 2 B y te s )
RAM Mapping rectly. Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through memory pointer registers (MP0 or MP1).
Rev. 1.10
7
June 29, 2007
HT82A822R
Indirect Addressing Register Locations 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation on [00H] ([02H]) will access the data memory pointed to by MP0 (MP1). Reading location 00H (02H) indirectly will return the result 00H. Writing indirectly results in no operation. The function of data movement between two indirect addressing registers is not supported. The memory pointer registers (MP0 and MP1) are 8-bit registers used to access the RAM by combining corresponding indirect addressing registers. Bank Pointer The bank pointer is used to assign the accessed RAM bank. When the users want to access the RAM bank 0, a 0 should be loaded onto BP. RAM locations before 40H in any bank are overlapped. Accumulator The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ ....)
Status Register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results from those intended. The TO flag can be affected only by a system power-up, a WDT time-out or executing the CLR WDT or HALT instruction. The PDF flag can be affected only by executing the HALT or CLR WDT instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, upon entering the interrupt sequence or executing a subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Interrupt The device provides USB interrupt and internal timer/event counter interrupts. The Interrupt Control Register0 (INTC0;0BH) contains the interrupt control bits that are used to set the enable/disable status and interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only Function
The ALU not only saves the results of a data operation but also changes the status register. Bit No. 0 Label C
C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared by a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register
1 2 3 4 5 6~7
AC Z OV PDF TO 3/4
Rev. 1.10
8
June 29, 2007
HT82A822R
the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at a specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. The USB interrupts are triggered by the following USB events and the related interrupt request flag (USBF; bit 4 of the INTC0) will be set.
* Access of the corresponding USB FIFO from PC * The USB suspend signal from PC * The USB resume signal from PC * USB Reset signal
The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (bit 5 of INTC0), caused by a timer 0 overflow. When the interrupt is enabled, the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further interrupts. The internal Timer/Even Counter 1 interrupt is initialized by setting the Timer/Event Counter 1 interrupt request flag (bit 6 of INTC0), caused by a timer 1 overflow. When the interrupt is enabled, the stack is not full and the T1F is set, a subroutine call to location 0CH will occur. The related interrupt request flag (T1F) will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, RET or RETI may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. No. a b c Interrupt Source USB interrupt Timer/Event Counter 0 overflow Timer/Event Counter 1 overflow Priority Vector 1 2 3 04H 08H 0CH
When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (USBF) and EMI bits will be cleared to disable other interrupts. When PC Host access the FIFO of the HT82A822R, the corresponding request bit of USR is set, and a USB interrupt is triggered. So user can easy to decide which FIFO is accessed. When the interrupt has been served, the corresponding bit should be cleared by firmware. When HT82A822R receive a USB Suspend signal from Host PC, the suspend line (bit0 of USC) of the HT82A822R is set and a USB interrupt is also triggered. When the HT82A822R receives a Resume signal from the Host PC, the resume line (bit3 of the USC) of the HT82A822R are set and a USB interrupt is triggered. Also when HT82A822R receive a Resume signal from Host PC, the resume line (bit3 of USC) of HT82A822R is set and a USB interrupt is triggered. Bit No. 0 1 2 3 4 5 6 7 Label EMI EUI ET0I ET1I USBF T0F T1F 3/4
It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the CALL operates in the interrupt subroutine.
Function Controls the master (global) interrupt (1=enable; 0=disable) Controls the USB interrupt (1=enable; 0= disable) Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable) Controls the Timer/Event Counter 1 interrupt (1=enable; 0=disable) USB interrupt request flag (1=active; 0=inactive) Internal Timer/Event Counter 0 request flag (1:active; 0:inactive) Internal Timer/Event Counter 1 request flag (1:active; 0:inactive) Unused bit, read as 0 INTC0 (0BH) Register
Rev. 1.10
9
June 29, 2007
HT82A822R
Oscillator Configuration There is an oscillator circuit in the microcontroller.
OSCI
The WDT OSC period is typical 65ms. This time-out period may vary with temperature, VDD and process variations. The WDT OSC always works for any operation mode. If the instruction clock is selected as the WDT clock source, the WDT operates in the same manner except in the halt mode. In the mode, the WDT stops counting and lose its protecting purpose. In this situation the logic can only be re-started by external logic. The high nibble and bit3 of the WDTS are reserved for user defined flags, which can be used to indicate some specified status. The WDT overflow under normal operation initializes a chip reset and sets the status bit TO. In the HALT mode, the overflow initializes a warm reset, and only the PC and SP are reset to zero. To clear the contents of the WDT, there are three methods to be adopted, i.e., external reset (a low level to RESET), software instruction, and a HALT instruction. There are two types of software instructions; CLR WDT and the other set CLR WDT1 and CLR WDT2. Of these two types of instruction, only one type of instruction can be active at a time depending on the options CLR WDT times selection option. If the CLR WDT is selected (i.e., CLR WDT times equal one), any execution of the CLR WDT instruction clears the WDT. In the case that CLR WDT1 and CLR WDT2 are chosen (i.e., CLR WDT times equal two), these two instructions have to be executed to clear the WDT; otherwise, the WDT may reset the chip due to time-out.
W DT OSC S y s te m C lo c k /4
M ask O p tio n S e le c t W D T P r e s c a le r 8 - b it C o u n te r 7 - b it C o u n te r
OSCO C r y s ta l O s c illa to r
System Oscillator This oscillator is designed for system clocks. The HALT mode stops the system oscillator and ignores an external signal to conserve power. A crystal across OSCI and OSCO is needed to provide the feedback and phase shift required for the oscillator. No other external components are required. Instead of a crystal, a resonator can also be connected between OSCI and OSCO to get a frequency reference, but two external capacitors in OSCI and OSCO are required. The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator still works. The WDT oscillator can be disabled by ROM code option to conserve power. Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or a instruction clock (system clock/4). The timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The WDT can be disabled by options. But if the WDT is disabled, all executions related to the WDT lead to no operation. When the WDT clock source is selected, it will be first divided by 256 (8-stage) to get the nominal time-out period. By invoking the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 can give different time-out periods. Bit No. Label
W S0~W S2
8 -to -1 M U X W D T T im e - o u t
Watchdog Timer
Function Watchdog Timer division ratio selection bits Bit 2,1,0 = 000, division ratio = 1:1 Bit 2,1,0 = 001, division ratio = 1:2 Bit 2,1,0 = 010, division ratio = 1:4 Bit 2,1,0 = 011, division ratio = 1:8 Bit 2,1,0 = 100, division ratio = 1:16 Bit 2,1,0 = 101, division ratio = 1:32 Bit 2,1,0 = 110, division ratio = 1:64 Bit 2,1,0 = 111, division ratio = 1:128 Unused bit, read as 0 Test mode setting bits (T3, T2, T1, T0)=(0, 1, 0, 1), enter DAC write mode. Otherwise normal operation. WDTS (09H) Register
0 1 2
WS0 WS1 WS2
3 7~4
3/4 T3~T0
Rev. 1.10
10
June 29, 2007
HT82A822R
Power Down Operation - HALT The HALT mode is initialized by the HALT instruction and results in the following:
* The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is selected). * The contents of the on-chip RAM and registers remain unchanged.
* The WDT and WDT prescaler will be cleared and re-
The WDT time-out during HALT is different from other chip reset conditions, since it can perform a warm re set that resets only the program counter and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets. TO PDF 0 u 0 1 1 0 u 1 u 1 RESET Conditions RESET reset during power-up RESET reset during normal operation RESET wake-up HALT WDT time-out during normal operation WDT wake-up HALT
counted again (if the WDT clock is from the WDT oscillator). * All of the I/O ports remain in their original status.
* The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a warm reset. After the TO and PDF flags are examined, the cause for chip reset can be determined. The PDF flag is cleared by a system power-up or executing the CLR WDT instruction and is set when executing the HALT instruction. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the program counter and SP; the others remain in their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake-up the device by mask option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it awakens from an interrupt, two sequence may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period will be inserted after a wake-up. If the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. Reset There are four ways in which a reset can occur:
* RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation * USB reset
Note: u stands for unchanged To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra delay of 1024 system clock pulses when the system resets (power-up, WDT time-out or RES reset) or the system awakes from the HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will enable the SST delay.
V
DD
RESET
Reset Circuit
VDD RES S S T T im e - o u t C h ip R eset tS
ST
Reset Timing Chart
HALT W DT
RESET
W a rm
R eset
OSCI
SST 1 0 - b it R ip p le C o u n te r S y s te m R eset
C o ld R eset
Reset Configuration
Rev. 1.10
11
June 29, 2007
HT82A822R
The functional unit chip reset status are shown below. Program Counter Interrupt WDT Timer/event Counter Input/output Ports Stack Pointer 000H Disable Clear. After master reset, WDT begins counting Off Input mode Points to the top of the stack
The registers status are summarized in the following table. Reset (Power On) xxxx xxxx xxxx xxxx xxxx xxxx 000H xxxx xxxx -xxx xxxx 0000 0111 --00 xxxx -000 0000 xxxx xxxx xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx x010 xxxx xxxx WDT Time-out (Normal Operation) uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu 0000 0111 --1u uuuu -000 0000 uuuu uuuu uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 uuxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu xxxx x010 uuuu uuuu RES Reset (Normal Operation) uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu 0000 0111 --uu uuuu -000 0000 uuuu uuuu uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 10xx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx x010 uuuu uuuu RES Reset (HALT) uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu 0000 0111 --01 uuuu -000 0000 uuuu uuuu uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 10xx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx x010 uuuu uuuu WDT Time-Out (HALT)* uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu uuuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uu-u u--uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 10xx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu xxxx x010 uuuu uuuu USB-Reset (Normal) uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu 0000 0111 --uu uuuu -000 0000 uuuu uuuu uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1000 0u00 00uu 0000 0u00 u000 0uu0 00uu 0000 0000 0000 0000 0u00 u000 0000 0000 xxxx x010 0000 0000 USB-Reset (HALT) uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu 0000 0111 --01 uuuu -000 0000 uuuu uuuu uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1000 0u00 00uu 0000 0u00 u000 0uu0 00uu 0000 0000 0000 0000 0u00 u000 0000 0000 xxxx x010 0000 0000
Register
MP0 MP1 ACC Program Counter TBLP TBLH WDTS STATUS INTC0 TMR0H TMR0L TMR0C TMR1H TMR1L TMR1C PA PAC PB PBC PC PCC USC USR UCC USF AWR STALL SIES MISC SETIO FIFO0
Rev. 1.10
12
June 29, 2007
HT82A822R
Reset (Power On) xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 WDT Time-out (Normal Operation) uuuu uuuu uuuu uuuu 0000 0000 0000 0000 0000 0000 RES Reset (Normal Operation) uuuu uuuu uuuu uuuu 0000 0000 0000 0000 0000 0000 RES Reset (HALT) uuuu uuuu uuuu uuuu 0000 0000 0000 0000 0000 0000 WDT Time-Out (HALT)* uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu USB-Reset (Normal) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 USB-Reset (HALT) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Register
FIFO1 FIFO2 DAC_LIMIT_L DAC_LIMIT_H DAC_WR
Note: * stands for warm reset u stands for unchanged x stands for unknown _ stands for undefined
Timer/Event Counter Two timer/event counters (TMR0, TMR1) are implemented in the microcontroller. The timer/event counter 0/1 contains a 16-bit programmable count-up counter and the clock may come from an external source or an internal clock source. An internal clock source comes from fSYS/4. The external clock input allows the user to count external events, measure time intervals or pulse widths, or to generate an accurate time base. There are six registers related to the Timer/Event Counter 0; TMR0H (0CH), TMR0L (0DH), TMR0C (0EH) and the Timer/Event Counter 1; TMR1H (0FH), TMR1L (10H), TMR1C (11H). For 16-bit timer to write data to TMR0/1L will only put the written data to an internal lower-order byte buffer (8-bit) and writing TMR0/1H will transfer the specified data and the contents of the lower-order byte buffer to TMR0/1H and TMR0/1L registers. The Timer/Event Counter 0/1 preload register is changed by each writing TMR0/1H operations. Reading TMR0/1H will latch the contents of TMR0/1H and TMR0/1L counters to the destination and the lower-order byte buffer, respectively. Reading the TMR0/1L will read the contents of the lower-order byte buffer. The TMR0/1C is the Timer/Event Counter 0/1 control register, which defines the operating mode, counting enable or disable and an active edge. The TM0 and TM1 bits define the operation mode. The event count mode is used to count external events, which means that the clock source is from an external (TMR0, TMR1) pin. The timer mode functions as a normal timer with the clock source coming from the internal clock source. Finally, the pulse width measurement mode can be used to count the high level or low level duration of the external signal (TMR0, TMR1), and the counting is based on the internal clock source. In the event count or timer mode, the timer/event counter starts counting at the current contents in the timer/event counter and ends at FFFFH. Once an overflow occurs, the counter is reloaded from the timer/event
counter preload register, and generates an interrupt request flag (T0F; bit 5 of INTC0, T1F; bit 6 of INTC0). In the pulse width measurement mode with the values of the TON and TE bits equal to 1, after the TMR0 (TMR1) has received a transient from low to high (or high to low if the TE bit is 0), it will start counting until the TMR0 (TMR1) returns to the original level and resets the TON. The measured result remains in the timer/event counter even if the activated transient occurs again. In other words, only 1-cycle measurement can be made until the TON is set. The cycle measurement will re-function as long as it receives further transient pulse. In this operation mode, the timer/event counter begins counting not according to the logic level but to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. To enable the counting operation, the Timer ON bit (TON; bit 4 of TMR0C or TMR1C) should be set to 1. In the pulse width measurement mode, TON is automatically cleared after the measurement cycle is completed. But in the other two modes, the TON can only be reset by instructions. The overflow of the Timer/Event Counter 0/1 is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET0I or ET1I disables the related interrupt service. In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the timer/event counter is turn on, data written to the timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues its operation until an overflow occurs. When the timer/event counter (reading TMR0/TMR1) is read, the clock is blocked to avoid errors, as this may results in a counting error. Blocking of the clock should be taken into account by the programmer.
Rev. 1.10
13
June 29, 2007
HT82A822R
Bit No. 0~2, 5 Label 3/4 Unused bit, read as 0 Defines the TMR active edge of the timer/event counter In Event counter mode (TM1, TM0)=(0, 1): 1=count on falling edge; 0=count on rising edge In Pulse width measurement mode (TM1, TM0)=(1, 1): 1=start counting on the rising edge, stop on the falling edge; 0=start counting on the falling edge, stop on the rising edge Enable/disable the timer counting (0=disable; 1=enable) Defines the operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMRC (11H) Register Function
3
TE
4
TON
6 7
TM0 TM1
fS
Y S /4
f IN
T
D a ta B u s TM 1 TM 0 TE 1 6 B its T im e r /E v e n t C o u n te r P r e lo a d R e g is te r R e lo a d
T M R 0 /1
TM 1 TM 0 TON
P u ls e W id th M e a s u re m e n t M o d e C o n tro l
1 6 B its T im e r /E v e n t C o u n te r (T M R 0 /1 )
O v e r flo w to In te rru p t
Timer/Event Counter 0/1 Input/Output Ports There are 24 bidirectional input/output lines in the micro-controller, labeled from PA to PC, which are mapped to the data memory of [12H], [14H] or [16H], respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H or 16H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC or PCC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically (i.e. on-the-fly) under software control. To function as an input, the corresponding latch of the control register must write 1. The input source also depends on the control register. If the control register bit is 1 the input will read the pad state. If the control register bit is 0 the contents of the latches will move to the internal bus. The latter is possible in the Read-modify-write instruction. For output function, CMOS configurations can be selected. These control registers are mapped to locations 13H, 15H or 17H. After a chip reset, these input/output lines remain at high levels or floating state (depending on the pull-high options). Each bit of these input/output latches can be set or cleared by SET [m].i and CLR [m].i (m=12H, 14H or 16H) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. It is recommended that unused or not bonded out I/O lines should be set as output pins by software instruction to avoid consuming power under input floating state.
Rev. 1.10
14
June 29, 2007
HT82A822R
V
DD
D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
C o n tr o l B it P u ll- h ig h O p tio n Q D CK S Q
D a ta B it Q D CK S Q
PA PB PC PC PC PC
0~P 0~P 0 1 /T 2 /T 3~P
A7 B7 MR0 MR1 C7
W r ite D a ta R e g is te r
M R e a d D a ta R e g is te r S y s te m W a k e - u p ( P A o n ly ) T M R 0 fo r P C 1 T M R 1 fo r P C 2 U
X M a s k O p tio n
Input/Output Ports Low Voltage Reset - LVR (by ROM Code Option) The LVR option is 3.0V. The microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~VLVR such as changing a battery, the LVR will automatically reset the device internally. The LVR includes the following specifications:
* The low voltage (0.9V~VLVR) has to remain in their
and the Resume line (bit 3 of USC) is set. In order to make HT82A822R work properly, the firmware must set the USBCKEN (bit 3 of UCC) to 1 and clear the SUSP2 (bit4 of the UCC). Since the Resume signal will be cleared before the Idle signal is sent out by the host and the Suspend line (bit 0 of USC) is going to 0. So when the MCU is detecting the Suspend line (bit0 of USC), the Resume line should be remembered and token into consideration. The following is the timing diagram:
SUSPEND U S B R e s u m e S ig n a l
original state to exceed 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and do not perform a reset function.
* The LVR uses the OR function with the external
RESET signal to perform chip reset. Suspend Wake-Up and Remote Wake-Up If there is no signal on the USB bus for over 3ms, the HT82A822R will go into a suspend mode. The Suspend line (bit 0 of the USC) will be set to 1 and a USB interrupt is triggered to indicate that the HT82A822R should jump to the suspend state to meet the USB suspend current spec. In order to meet the suspend current, the firmware should disable the USB clock by clearing the USBCKEN (bit3 of the UCC) to 0. Also the user can further decrease the suspend current by set the SUSP2 (bit4 of the UCC). When the resume signal is sent out by the host, the HT82A822R will wake-up the MCU by USB interrupt
U S B _ IN T
The device with remote wake up function can wake-up the USB Host by sending a wake-up pulse through RMWK (bit 1 of USC). Once the USB Host receive the wake-up signal from HT82A822R, it will send a Resume signal to device. The timing as follow:
SUSPEND M in . 1 U S B C L K RMW K
M in .2 .5 m s
U S B R e s u m e S ig n a l
U S B _ IN T
Rev. 1.10
15
June 29, 2007
HT82A822R
USB Interface The HT82A822R have 3 Endpoints (EP0 ~EP2). EP0 supports Control transfer. EP1 supports Interrupt transfer. EP2 supports Isochronous transfer. These registers, including USC (20H), USR (21H), UCC (22H), AWR (23H), STALL (24H ), SIES (25H), MISC (26H), SETIO (27H), FIFO0 (28H), FIFO1 (29H), FIFO2 (2AH) used for the USB function. The FIFO size of each FIFO is 8 byte (FIFO0), 8 byte (FIFO1), 384 byte (FIFO2), and total are 400 bytes. URD (bit7 of USC) is USB reset signal control function definition bit. Bit No. 0 Label SUSP R/W R Reset 0 Functions Read only, USB suspend indication. When this bit is set to 1 (set by SIE), it indicates the USB bus enters suspend mode. The USB interrupt is also triggered on changing from low to high of this bit. USB remote wake-up command. It is set by MCU to force the USB host leaving the suspend mode. USB reset indication. This bit is set/cleared by USB SIE. This bit is used to detect USB reset event on USB bus. When this bit is set to 1, this indicates an USB reset is occurred and an USB interrupt will be initialized. USB resume indication. When the USB leaves suspend mode, this bit is set to 1 (set by SIE). When the RESUME is set by SIE, an interrupt will be generated to wake-up the MCU. In order to detecting the suspend state, MCU should set USBCKEN and clear SUSP2 (in UCC register) to enable the SIE detecting function. The RESUME will be cleared while the SUSP is going 0. When MCU is detecting the SUSP, the RESUME (causes MCU to wake-up) should be remembered and token into consideration. 0/1: Turn-off/on V33O output Undefined bit, read as 0. USB reset signal control function definition 1: USB reset signal will reset MCU 0: USB reset signal cannot reset MCU USC (20H) Register The USR (USB endpoint interrupt status register) register is used to indicate which endpoint is accessed and to select serial bus (USB). The endpoint request flags (EP0F, EP1F, EP2F) are used to indicate which endpoints are accessed. If an endpoint is accessed, the related endpoint request flag will be set to 1 and the USB interrupt will occur (if USB interrupt is enabled and the stack is not full). When the active endpoint request flag is served, the endpoint request flag has to be cleared to 0 by software. Bit No. 0 Label EP0F R/W R/W Reset 0 Functions When this bit is set to 1 (set by SIE). It indicates the endpoint 0 is accessed and an USB interrupt will occur. When the interrupt has been served, this bit should be cleared by software. When this bit is set to 1 (set by SIE). It indicates the endpoint 1 is accessed and an USB interrupt will occur. When the interrupt has been served, this bit should be cleared by software. When this bit is set to 1 (set by SIE). It indicates the endpoint 2 is accessed and an USB interrupt will occur. When the interrupt has been served, this bit should be cleared by software. Undefined bit, read as 0. USR (21H) Register
1
RMWK
R/W
0
2
URST
R/W
0
3
RESUME
R
0
4 5~6 7
V33O 3/4 URD
R/W 3/4 R/W
0 3/4 1
1
EP1F
R/W
0
2 3~7
EP2F 3/4
R/W 3/4
0 3/4
Rev. 1.10
16
June 29, 2007
HT82A822R
There is a system clock control register implemented to select the clock used in the MCU. This register consists of USB clock control bit (USBCKEN), second suspend mode control bit (SUSP2) and system clock selection (SYSCLK) And to define which endpoint FIFO is select by EPS2, EPS1 and EPS0. Bit No. Label R/W Reset Functions Accessing endpoint FIFO selection, EPS2, EPS1, EPS0: 000: Select endpoint 0 FIFO 001: Select endpoint 1 FIFO 010: Select endpoint 2 FIFO 011: reserved for future expansion, cannot be used 100: reserved for future expansion, cannot be used 101: reserved for future expansion, cannot be used 110: reserved for future expansion, cannot be used 111: reserved for future expansion, cannot be used If the selected endpoints are not existed, the related functions will be absent. USB clock control bit. When this bit is set to 1, it indicates that the USB clock is enabled. Otherwise, the USB clock is turned-off. This bit is used for reducing power consumption in suspend mode. In normal mode, clean this bit to 0 In HALT mode, set this bit to 1 for reducing power consumption. This bit is used to define the MCU system clock comes form external OSC or system clock comes PLL output 24MHz clock. 0: system clock comes from OSC 1: system clock comes from PLL output 24MHz This bit is used to specify the system clock oscillator frequency used by MCU. If a 6MHz crystal oscillator or resonator is used, this bit should be set to 1. If a 12MHz crystal oscillator or resonator is used. this bit should be cleared to 0. UCC (22H) Register Note: Isochronous endpoint 2 is implemented by hardware, so FIFO2 can not read/write by firmware. AWR register contains current address and a remote wake up function control bit. The initial value of AWR is 00H. The address value extracted from the USB command has not to be loaded into this register until the SETUP stage being finished. Bit No. 0 1~7 Label WKEN AD0~AD6 R/W R/W R/W Power-on 0 0 Functions USB remote-wake-up enable/disable (1/0) USB device address AWR (23H) Register STALL register shows where the corresponding endpoint works properly or not. As soon as the endpoint works improperly, the related bit in the STALL has to be set to 1. The STALL will be cleared by USB reset signal. Bit No. 0~2 3~7 Label STL0~STL2 STL3~STL7 R/W R/W 3/4 Power-on 0 0 Functions Set by users when related USB endpoints were stalled. They are cleared by USB reset and Setup Token event. Undefined bit, read as 0. STALL (24H) Register
0~2
EPS0~EPS2
R/W
0
3
USBCKEN
R/W
0
4
SUSP2
R/W
0
5
fSYS24MHz
R/W
0
6
SYSCLK
R/W
0
Rev. 1.10
17
June 29, 2007
HT82A822R
Bit No. Label R/W Power-on Functions This bit is used to configure the SIE automatically change the device address by the value stored in the AWR register. When this bit is set to 1 by firmware, the SIE will update the device address by the value stored in the AWR register after PC host is successfully read the data from device by IN operation. Otherwise, when this bit is cleared to 0, the SIE will update the device address immediately after an address is written to the AWR register. So, in order to work properly, firmware has to clear this bit after next valid SETUP token is received. This bit is used to indicate there are some errors occurred during the FIFO0 is accessed. This bit is set by SIE and should be cleared by firmware. This bit is used to indicate there are OUT token (except the OUT zero length token) has been received. The firmware clears this bit after the OUT data has been read. Also, this bit will be cleared by SIE after the next valid SETUP token is received. This bit is used to indicate the current USB receiving signal from PC host is IN token. This bit is used to indicate the SIE is transmitted NAK signal to host in response to PC host IN or OUT token. Error condition failure flag include CRC, PID, no integrate token error, CRCF will be set by hardware and the CRCF need to be cleared by firmware. Token package active flag, low active. NAK token interrupt mask flag. If this bit set, when device sent a NAK token to host, the interrupt will not happen. Otherwise when this bit is cleared, device sent a NAK token to host will enter the interrupt sub-routine. SIES (25H) Register MISC register combines a command and status to control desired endpoint FIFO action and to show the status of wanted endpoint FIFO. The MISC will be cleared by USB reset signal. Bit No. 0 Label REQUEST R/W R/W Power-on 0 Functions After setting others status of desired one, FIFO can be requested by setting this bit high active. After work has been done, this bit must be set low. To represent the direction and transition end MCU accesses, When being set logic 1, MCU wants to write data to FIFO. After the work being done, this bit must be set logic 0 before terminating request to represent transition end. For reading action, this bit must be set logic 0 to represent MCU want to read and must be set logic 1 after the work done. To represent MCU clear requested FIFO, even the FIFO is not ready. After clearing the FIFO, USB interface will send force_tx_err to tell Host that data under-run if Host want to read data. Undefined bit, read as 0. To enable the isochronous pipe interrupt. To show that the data in FIFO is setup command. This bit will last this state until next one entering the FIFO. To tell that the desired FIFO is ready to work. To tell that host sent a 0-sized packet to MCU. This bit must be cleared by read action to corresponding FIFO. USB MISC (26H) Register
0
ASET
R/W
0
1
ERR
R/W
0
2
OUT
R/W
0
3 4
IN NAK
R R
0 0
5 6
CRCF EOT
R/W R
0 1
7
NMI
R/W
0
1
TX
R/W
0
2 3 4 5 6 7
CLEAR 3/4 ISOENSETCMD READY LEN0
R/W R R/W R/W R R
0 0 0 0 0 0
Rev. 1.10
18
June 29, 2007
HT82A822R
Bit No. 0 1 2 3~7 Label DATATG* SETIO1** SETIO2** 3/4 R/W R/W R/W R/W 3/4 Power-on 0 1 0 3/4 Functions To toggle this bit, all the DATA token will send DATA0 first. Set endpoint1 input or output pipe (1/0), default input pipe(1) Set endpoint2 input or output pipe (1/0), default output pipe(0) Reserved
SETIO Register, USB Endpoint 1~Endpoint 2 Set IN/OUT Pipe Register Note: *USB definition: when host send a set Configuration, the Data pipe should send the DATA0 (about the Data toggle) first. So, when Device received a set configuration setup command, user need to toggle this bit for next data will send a Data0 first. **Only need to set the data pipe as a input pile or output pile. The purpose of this function is to avoid the host sent a abnormal IN or OUT token and make the endpoint disability. Bit No. 0 1 Label StartBit** FullBit** R/W R/W R/W Power-on 0 0 Functions Start load new iso data from FIFO, if ready the FullBit will be set If the FullBit is set to 1 by system represent the new iso data is load to Bank1~Bank4 RAM Bank1~Bank4 data mode selector 0: Spectrum (R+L)/2 1: L/R USF (1DH) Register
2
ModeSelect
R/W
0
S ta r tB it= 1
F u llB it= 1 Y S ta r tB it= 0
N
Read RAM
B ank1~B ank4
End
Reading RAM Bank1~Bank4 Flow Chart
Bit No. 0~6 7
Label USVC0~ USVC6 MUTE
R/W R/W R/W
Power-on 0 0 Volume control Bit0~Bit6 Mute control, low active.
Functions
USB Speaker Volume Control
Rev. 1.10
19
June 29, 2007
HT82A822R
* Bank1~Bank4 audio data format (16 bit (R) 8 bit)
15
14
13~2
1
0
Original 16 bit audio data (2s complement)
15
13
12~9
8
7
Truncate 16 bit audio data to 8-bit
* ModeSelect=0 (Spectrum, (R+L)/2)
RAM RAM RAM RAM B ank1 B ank2 B ank3 B ank4 1 2 8 B y te s 1 2 8 B y te s 1 2 8 B y te s 1 2 8 B y te s 5 1 2 S a m p le s
* ModeSelect=1 (L/R)
RAM RAM RAM RAM B ank1 B ank2 B ank3 B ank4 1 2 8 B y te s , L e ft C h a n n e l 1 2 8 B y te s , L e ft C h a n n e l 1 2 8 B y te s , R ig h t C h a n n e l 1 2 8 B y te s , R ig h t C h a n n e l 2 5 6 L e ft C h a n n e l S a m p le s 2 5 6 R ig h t C h a n n e l S a m p le s
Result (dB) 6 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -0.5 -1 -1.5
USVC 000_1100 000_1011 000_1010 000_1001 000_1000 000_0111 000_0110 000_0101 000_0100 000_0011 000_0010 000_0001 000_0000 111_1111 111_1110 111_1101
Result (dB) -2 -2.5 -3 -3.5 -4 -4.5 -5 -5.5 -6 -6.5 -7 -7.5 -8 -8.5 -9 -9.5
USVC 111_1100 111_1011 111_1010 111_1001 111_1000 111_0111 111_0110 111_0101 111_0100 111_0011 111_0010 111_0001 111_0000 110_1111 110_1110 110_1101
Result (dB) -10 -10.5 -11 -11.5 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23
USVC 110_1100 110_1011 110_1010 110_1001 110_1000 110_0111 110_0110 110_0101 110_0100 110_0011 110_0010 110_0001 110_0000 101_1111 101_1110 101_1101
Result (dB) -24 -25 -26 -27 -28 -29 -30 -31 -32 3/4 3/4 3/4 3/4 3/4 3/4 3/4
USVC 101_1100 101_1011 101_1010 101_1001 101_1000 101_0111 101_0110 101_0101 101_0100 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Speaker mute control: MUTE= 0: Mute speaker output. MUTE= 1: Normal. Registers FIFO0~ FIFO2 R/W R/W Power-on xxH Functions EPi accessing register (i = 0~2). When an endpoint is disabled, the corresponding accessing register should be disabled. USB Endpoint Accessing Registers Definitions
Rev. 1.10
20
June 29, 2007
HT82A822R
DAC_Limit_L and DAC_Limit_H are used to define the 16-bit DAC output limit. DAC_Limit_L and DAC_Limit_H are unsigned value. If the 16-bit data from Host over the range defined by DAC_Limit_L and DAC_Limit_H, the output digital code to DAC will be clamp. DAC_Limit_L DAC_Limit_H Setting DAC output limit value example: ;----------------------------------------------------------; DAC Limit POR Value=8000H ; Set DAC Limit Value=FF00H ;----------------------------------------------------------clr [02DH] ; Set DAC Limit low byte=00H set [02EH] ; Set DAC Limit high byte=FFH ;----------------------------------------------------------In order to prevent the pop noise of speaker output, power amplifier should be output at the value of VDD/2 (send 8000H to DAC) during the initial power on state. If software set high then clear the bit DAC_WR_TRIG (bit 3 of DAC_WR register), the value on the DAC_Limit_L and DAC_Limit_H registers will write to DAC. Bit No. 0~2, 4~7 3 Label 3/4 DAC_WR_TRIG R/W R R/W Power-on 0 0 Functions Undefined bit, read as 0. DAC write trigger bit DAC output limit low byte DAC output limit high byte
DAC_WR (2FH) Register Example to avoid popping noise: System_Initial: ;----------------------------------------------------------; Avoid Pop Noise ;----------------------------------------------------------mov a,WDTS mov FIFO_TEMP,a ;Save WDTS value mov a,01010000b andm a,WDTS mov a,01010000b orm a,WDTS ;Enter DAC Write Data mode, high nibble of WDTS=0101b clr [02DH] ;Set DAC data low byte=00H mov a,80H mov [02EH],a ;Set DAC data high byte=80H nop ;Write 8000H to DAC set [02FH].3 nop clr [02FH].3 nop ;----------------------------------------------------------mov a,FIFO_TEMP ;Restore WDTS value mov WDTS,a ;Quit DAC Write Data mode ;----------------------------------------------------------Note: At DAC write data mode (high nibble of WDTS register is 0101b), DAC_Limit_L and DAC_Limit_H registers will be the 16-bit DAC input data register at falling edge of DAC_WR_TRIG. Otherwise, these two registers are used to define the 16-bit DAC output limit.
Rev. 1.10
21
June 29, 2007
HT82A822R
Configuration Options The following table shows all kinds of OTP option in the microcontroller. All of the OTP options must be defined to ensure proper system functioning. No. 1 2 3 4 5 6 7 8 9 Options PA0~PA7 pull-high resistor enabled or disabled (by bit) LVR enable or disable WDT enable or disable WDT clock source: fSYS/4 or WDTOSC CLRWDT instruction(s): 1 or 2 PA0~PA7 wake-up enabled or disabled (by bit) PB0~PB7 pull-high resistor enabled/disabled (by nibble) PC0~PC7 pull-high resistor enabled/disabled (by nibble) TBHP enable or disable (default disable)
Application Circuits
J1 U S B -B T y p e 1 2 3 4 5 L4 Bead 2 1 2 1 D+ DVSS FB1 AVDD 33W DVDD
10mF
33W 33W
0 .1 m F
0 .1 m F
1 .5 k W USBDN V33O USBDP PA3 PA2 PA1 PA0 AVDD2 ROUT LO UT AVSS2 AVSS1 B IA S AVDD1 DVSS3 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 9 8 7 L 5 B e a d F e r r ite 1 2 L 6 B e a d F e r r ite 6 5 4 3 2 1 PA3 PA2 PA1 PA0 AVDD2 ROUT LO UT AVSS2 AVSS1 B IA S AVDD1 DVSS3 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 DVSS2
U1 PA4 PA5 PA6 PA7 DVSS1 V33O USBDP USBDN DVDD1 RESET OSCO OSCI NC NC NC NC NC NC PC0 PC1 PC2 PC3 PC4 DVDD2
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
PA4 PA5 PA6 PA7 DVSS1 V33O USBDP USBDN DVDD1 RESET OSCO OSCI NC NC NC NC NC NC PC0 PC1 PC2 PC3 PC4 DVDD2 47kW Y1 12M H z VO LED 1 VPRE AVDD4 VSS IR E F NDO VADJ AVDD4 VF VR PB7 PB6 PB5 PB4 PB3 PB2 PB1 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1 HD1
0 .1 m F
47pF
47pF
10mF
100kW SW 1 R eset
DVDD
10mF
AVDD 1 L2 2
0 .1 m F
AVDD1
B e a d F e r r ite L3 1 2
10mF
AVDD
AVDD2
0 .1 m F
B e a d F e r r ite
10mF
AVDD
1
L7 2
AVDD4
0 .1 m F
PC5 DVSS2
B e a d F e r r ite
10mF
H T82A 822R
VR PA0 PA1 PA2 PA3 1 1 PA4 SW 2 SW 3 SW 4 SW 5 2 2 SW 6 AVDD4 L1 33m LO UT ROUT AVSS2 1 3 4 VADJ 1 .2 4 V 1 D1 3 10pF 470kW
100mF 0 .1 m F
VF
4 .7 m F
76kW
PB0 AVDD4 VSS SP AVDD4 PC0
J5 3 2 P h o n e ja c k S te r e o 1
100mF 100mF
VO LED 1
12V
PC1 PC2 PC3 PC4 AVDD4 VSS AVDD4 AVDD4
S C H O T T K Y D IO D E (S S 1 2 )
NDO
51kW
HT16A102
Rev. 1.10
22
June 29, 2007
HT82A822R
Instruction Set
Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be CLR PCL or MOV PCL, A. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Rev. 1.10
23
June 29, 2007
HT82A822R
Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the SET [m].i or CLR [m].i instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] INCA [m] INC [m] DECA [m] DEC [m]
Description
Cycles
Flag Affected
Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory
1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 1 1Note 1 1Note
Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Logic Operation
Increment & Decrement
Rev. 1.10
24
June 29, 2007
HT82A822R
Mnemonic Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Description Cycles Flag Affected
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
Rev. 1.10
25
June 29, 2007
HT82A822R
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Operation Affected flag(s) ADD A,x Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ACC + [m] + C OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. ACC ACC + [m] OV, Z, AC, C Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ACC + x OV, Z, AC, C Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ACC + [m] OV, Z, AC, C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ACC AND [m] Z
Rev. 1.10
26
June 29, 2007
HT82A822R
CALL addr Description Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack Program Counter + 1 Program Counter addr None Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] 00H None Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i 0 None Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF
Operation Affected flag(s) CLR [m] Description Operation Affected flag(s) CLR [m].i Description Operation Affected flag(s) CLR WDT Description Operation
Affected flag(s) CLR WDT1 Description
Operation
Affected flag(s) CLR WDT2 Description
Operation
Affected flag(s)
Rev. 1.10
27
June 29, 2007
HT82A822R
CPL [m] Description Operation Affected flag(s) CPLA [m] Description Complement Data Memory Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC [m] Z Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ACC + 00H or [m] ACC + 06H or [m] ACC + 60H or [m] ACC + 66H C Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] [m] - 1 Z Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] - 1 Z Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO 0 PDF 1 TO, PDF
Operation Affected flag(s) DAA [m] Description
Operation
Affected flag(s) DEC [m] Description Operation Affected flag(s) DECA [m] Description Operation Affected flag(s) HALT Description
Operation Affected flag(s)
Rev. 1.10
28
June 29, 2007
HT82A822R
INC [m] Description Operation Affected flag(s) INCA [m] Description Operation Affected flag(s) JMP addr Description Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] [m] + 1 Z Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] + 1 Z Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter addr None Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC [m] None Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC x None Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ACC None No operation No operation is performed. Execution continues with the next instruction. No operation None Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR [m] Z
Operation Affected flag(s) MOV A,[m] Description Operation Affected flag(s) MOV A,x Description Operation Affected flag(s) MOV [m],A Description Operation Affected flag(s) NOP Description Operation Affected flag(s) OR A,[m] Description Operation Affected flag(s)
Rev. 1.10
29
June 29, 2007
HT82A822R
OR A,x Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) RET A,x Description Operation Affected flag(s) RETI Description Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ACC OR [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter Stack None Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter Stack ACC x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit (bit 0; register INTC). If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter Stack EMI 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 [m].7 None
Operation Affected flag(s) RL [m] Description Operation Affected flag(s) RLA [m] Description
Operation Affected flag(s)
Rev. 1.10
30
June 29, 2007
HT82A822R
RLC [m] Description Operation Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 C C [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 C C [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 C C [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 C C [m].0 C
Affected flag(s) RLCA [m] Description
Operation
Affected flag(s) RR [m] Description Operation Affected flag(s) RRA [m] Description
Operation Affected flag(s) RRC [m] Description Operation
Affected flag(s) RRCA [m] Description
Operation
Affected flag(s)
Rev. 1.10
31
June 29, 2007
HT82A822R
SBC A,[m] Description Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] - C OV, Z, AC, C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] - C OV, Z, AC, C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] - 1 Skip if [m] = 0 None Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC [m] - 1 Skip if ACC = 0 None Set Data Memory Each bit of the specified Data Memory is set to 1. [m] FFH None Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i 1 None
Operation Affected flag(s) SBCM A,[m] Description
Operation Affected flag(s) SDZ [m] Description
Operation Affected flag(s) SDZA [m] Description
Operation Affected flag(s) SET [m] Description Operation Affected flag(s) SET [m].i Description Operation Affected flag(s)
Rev. 1.10
32
June 29, 2007
HT82A822R
SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] + 1 Skip if [m] = 0 None Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] + 1 Skip if ACC = 0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] OV, Z, AC, C Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] OV, Z, AC, C Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - x OV, Z, AC, C
Operation Affected flag(s) SIZA [m] Description
Operation Affected flag(s) SNZ [m].i Description
Operation Affected flag(s) SUB A,[m] Description
Operation Affected flag(s) SUBM A,[m] Description
Operation Affected flag(s) SUB A,x Description
Operation Affected flag(s)
Rev. 1.10
33
June 29, 2007
HT82A822R
SWAP [m] Description Operation Affected flag(s) SWAPA [m] Description Operation Affected flag(s) SZ [m] Description Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 [m].7 ~ [m].4 None Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3 ~ ACC.0 [m].7 ~ [m].4 ACC.7 ~ ACC.4 [m].3 ~ [m].0 None Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m] = 0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] Skip if [m] = 0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i = 0 None Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None
Operation Affected flag(s) SZA [m] Description
Operation Affected flag(s) SZ [m].i Description
Operation Affected flag(s) TABRDC [m] Description Operation Affected flag(s) TABRDL [m] Description Operation Affected flag(s)
Rev. 1.10
34
June 29, 2007
HT82A822R
XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ACC XOR [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR x Z
Rev. 1.10
35
June 29, 2007
HT82A822R
Package Information
48-pin SSOP (300mil) Outline Dimensions
48 A
25 B
1 C C'
24
G H a F
D E
Symbol A B C C D E F G H a
Dimensions in mil Min. 395 291 8 613 85 3/4 4 25 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 25 3/4 3/4 3/4 3/4 Max. 420 299 12 637 99 3/4 10 35 12 8
Rev. 1.10
36
June 29, 2007
HT82A822R
Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SSOP 48W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301 1000.1 13+0.5 -0.2 20.5 32.2+0.3 -0.2 38.20.2
Rev. 1.10
37
June 29, 2007
HT82A822R
Carrier Tape Dimensions
D
E F W C B0
P0
P1
t
D1
P K2 A0
K1
SSOP 48W Symbol W P E F D D1 P0 P1 A0 B0 K1 K2 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 320.3 160.1 1.750.1 14.20.1 2 Min. 1.5+0.25 40.1 20.1 120.1 16.20.1 2.40.1 3.20.1 0.350.05 25.5
Rev. 1.10
38
June 29, 2007
HT82A822R
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 86-21-6485-5560 Fax: 86-21-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2007 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.10
39
June 29, 2007

▲Up To Search▲

Price & Availability of HT82A822R07

	To Download HT82A822R07 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .